Many digital devices from the simplest gate array to the most complex circuit board can require one or more clocks, and one or more clocking signals, for a variety of routine and critical processes. An example of a critical process is the feeding of signals from a processor to a bus. Without a precise timing mechanism, synchronizing the signals in the bus would be impossible.
Another example is in memory arrays where nodes are pre-charged to a specific logic level. A clock signal is applied to access these nodes or to perform some other function. One concern circuit designers have is that if the clock signal is in the ‘high’ state for too long a duration, it can discharge these pre-charged nodes or cause charge sharing between nodes and the logic value can be lost. Therefore, the goal is to limit the maximum pulse width of such signals that operate on latches, memory, etc.
Duty cycle distortion (DCD) and pulse-width distortion (PWD) are different names for the same problem. PWD can be defined as the difference between the pulse width of a ‘high’ output (representing a “1”) and the pulse width of a ‘low’ output (representing a “0”). PWD causes a distortion in the eye diagram, where the eye crossings are offset up or down from the vertical midpoint of the eye. (In digital communications, the “eye diagram” is used to visualize how the waveforms used to send multiple bits of data can potentially lead to errors in the interpretation of those bits).
PWD can be quantified by driving the system with a clock-like pattern (such as 1 0 1 0 . . . ), measuring the width of the ‘high’ and ‘low’ pulses, and then using the following equation:
  PWD  =            [                        (                      longer            ⁢                                                  ⁢            pulse                    )                -                  (                      shorter            ⁢                                                  ⁢            pulse                    )                    ]        2  The most common causes of PWD are voltage offsets between the differential inputs and differences between the rise and fall times in the system.
Deviation from a reference standard, usually expressed in ±ps (plus or minus picoseconds), can occur on the leading edge or the trailing edge of a signal. PWD can be induced and coupled onto a clock signal from many different sources and is usually not uniform over all frequencies. Excessive PWD can increase the bit error rate (BER) of a communication signal by incorrectly transmitting the data bit stream. This leads to a violation of frequency and amplitude, causing partial or complete circuit failure.
Previous attempts to solve PWD problems center on pulse width modulation (PWM), space vector modulation (SVM), feedback loops or signal clamping. Typically, these solutions contain a large number of discrete devices, and require one subsystem for controlling the pulse width and another for limiting the duty cycle. As a result, additional latency (time delay) is introduced in the overall circuit, offsetting some the gains in signal quality.
The newest generations of ultra high density circuits also mandate lower device counts because of the requirements for additional system features in the architecture, the emphasis on lower power usage at increasing frequencies, and the inevitable power dissipation (heat) problems. Problems of current leakage, capacitance and signal contamination are magnified in all superscalar architectures.
As a result, there is a need for a pulse width limiting method for maintaining peak clock performance that solves some of the limitations of previous designs. The ideal circuit would solve the pulse width problem and reduce the device count, all without substantial change to the system architecture. Limiting the number of devices also allows for an increase in clock frequency, and higher frequency clocks are more efficient.